Wiring requirement and three-dimensional integration of field-programmable gate arrays
Proceedings of the 2001 international workshop on System-level interconnect prediction
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Design, layout and verification of an FPGA using automated tools
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Efficient tree topology for FPGA interconnect network
Proceedings of the 18th ACM Great Lakes symposium on VLSI
FPGA interconnect topologies exploration
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
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An innovative 3D physical design exploration methodology for Tree-based FPGA architecture is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multidimensional network with the logic unites and switch blocks placed at different levels, using a Butterfly-Fat Tree network topology. A 3D physical design exploration methodology leverage on Through Silicon Via (TSVs) using a horizontal break-point to re-distribute the Tree interconnects into multiple stacked active silicon layers proposed in this paper.