Field-programmable gate arrays
Field-programmable gate arrays
On routability prediction for field-programmable gate arrays
DAC '93 Proceedings of the 30th international Design Automation Conference
A method for generating random circuits and its application to routability measurement
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Three dimensional metallization for vertically integrated circuits
Microelectronic Engineering
System-level performance evaluation of three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Rothko: A Three-Dimensional FPGA
IEEE Design & Test
Reconfigurable architectures for general-purpose computing
Reconfigurable architectures for general-purpose computing
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
Proceedings of the 2005 international workshop on System level interconnect prediction
Three-dimensional place and route for FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Designing a 3-D FPGA: switch box architecture and thermal issues
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Physical design exploration of 3D tree-based FPGA architecture
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA)
Proceedings of the 10th FPGAworld Conference
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In this paper analytical models for predicting interconnect require冒ments in field-programmable gate arrays (FPGAs) are presented, and opportunities for 3-D implementation of FPGAs are examined. The analytical models for 2-D FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with 20K 4-input look-up tables, the reduction in channel width, interconnect delay, and power dissipation can be over 50% by 3-D implementation.