The triptych FPGA architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 1997 international symposium on Physical design
Universal switch blocks for three-dimensional FPGA design
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Detailed routing architectures for embedded programmable logic IP cores
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Wiring requirement and three-dimensional integration of field-programmable gate arrays
Proceedings of the 2001 international workshop on System-level interconnect prediction
Design and analysis of a dynamically reconfigurable three-dimensional FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
On optimum switch box designs for 2-D FPGAs
Proceedings of the 38th annual Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Rothko: A Three-Dimensional FPGA
IEEE Design & Test
Partition-driven standard cell thermal placement
Proceedings of the 2003 international symposium on Physical design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A New Switch Block for Segmented FPGAs
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Architectures and algorithms for field-programmable gate arrays with embedded memory
Architectures and algorithms for field-programmable gate arrays with embedded memory
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
Proceedings of the 2005 international workshop on System level interconnect prediction
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
Monitoring Temperature in FPGA based SoCs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Placement and Routing in 3D Integrated Circuits
IEEE Design & Test
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Performance benefits of monolithically stacked 3D-FPGA
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Three-dimensional place and route for FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Thermal Trends in Emerging Technologies
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Thermal via planning for 3-D ICs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Switch Box Architectures for Three-Dimensional FPGAs
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Thermal characterization and optimization in platform FPGAs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Proceedings of the great lakes symposium on VLSI
Interlaced switch boxes placement for three-dimensional FPGA architecture design
International Journal of Circuit Theory and Applications
Performance analysis and optimization of high density tree-based 3d multilevel FPGA
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
A novel 3-D FPGA architecture targeting communication intensive applications
Journal of Systems Architecture: the EUROMICRO Journal
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Three-dimensional (3-D) integration is an attractive technology to reduce wirelengths in a field-programmable gate array (FPGA). However, it suffers from two problems: one, the inter-layer vias are limited in number, and second, the increased power density leads to high junction temperatures. In this paper, we tackle the first problem by designing switch boxes that maximize the use of the vias. Compared to the previously used subset switch box, our best switch box reduces the number of vias by about 49% and area-delay product by about 9%. For the second problem, we utilize the difference in power densities between CLBs and some of the hard blocks in modern FPGAs to distribute the power more uniformly across the FPGA. The peak temperature in a two-layer FPGA reduces by about 16°C after our change.