Performance analysis and optimization of high density tree-based 3d multilevel FPGA

Authors:
Vinod Pangracious;Zied Marrakchi;Emna Amouri;Habib Mehrez
Affiliations:
Laboratory d'Informatique de Paris 6, University of Pierre et Marie Curie, Paris, France;Flexras Technologies, Paris, France;Laboratory d'Informatique de Paris 6, University of Pierre et Marie Curie, Paris, France;Laboratory d'Informatique de Paris 6, University of Pierre et Marie Curie, Paris, France
Venue:
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
Year:
2013

Citing 9
Cited 1

Design and analysis of a dynamically reconfigurable three-dimensional FPGA

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Architecture and CAD for Deep-Submicron FPGAs

Architecture and CAD for Deep-Submicron FPGAs
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation

Proceedings of the 2003 international workshop on System-level interconnect prediction
VPR: A new packing, placement and routing tool for FPGA research

FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Placement and Routing in 3D Integrated Circuits

IEEE Design & Test
Performance benefits of monolithically stacked 3D-FPGA

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Efficient tree topology for FPGA interconnect network

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Designing a 3-D FPGA: switch box architecture and thermal issues

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA interconnect topologies exploration

International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08

High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA)

Proceedings of the 10th FPGAworld Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

A Tree-based 3D Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multilevel network with the switch blocks placed at different tree levels using Butterfly-Fat-Tree network topology. Two dimensional layout development of a Tree-based multilevel interconnect is a major challenge for Tree-based FPGA. A 3D interconnect network technology leverage on Through Silicon Via (TSVs) to re-distribute the Tree interconnects, based on network delay and thermal considerations into multiple silicon layers is discussed. The impact of of Through Silicon Vias and performance improvement of 3D Tree-based FPGA are analyzed. We present an optimized physical design technology leverage on TSV, Thermal-TSV (TTSV), and thermal analysis. Compared to 3D Mesh-based FPGA, the 3D Tree-based FPGA design reduces the number of TSVs by 29% and leads to a performance improvement of 53% based on our place and route experiments.