Design and analysis of a dynamically reconfigurable three-dimensional FPGA

Authors:
Silviu Chiricescu;Miriam Leeser;M. Michael Vai
Affiliations:
DigitalDNA systems Architecture Lab., Motorola Inc., Schaumburg, IL;Northeastern Univ., Boston, MA;Northeastern Univ., Boston, MA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Year:
2001

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Abstract

This paper presents the design and analysis of a dynamically reconfigurable field programmable gate array (FPGA) that consists of three physical layers: routing and logic block layer, routing layer, and memory layer. The architecture was developed using a methodology that examines different architectural parameters and how they affect different performance criteria such as speed, area, and reconfiguration time. The resulting architecture has high performance while the requirement of balancing the areas of its constituent layers is satisfied.