DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Routing in a Three-Dimensional Chip
IEEE Transactions on Computers
Universal switch blocks for three-dimensional FPGA design
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Design and analysis of a dynamically reconfigurable three-dimensional FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Rothko: A three dimensional FPGA architecture, its fabrication, and design tools
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Architectural Design of a Three Dimensional FPGA
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
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We present a multilevel routing algorithm for circuits modeled on the 3-Dimensional grid. The algorithm repeatedly contracts the grid by coalescing nodes until a small manageable size has been obtained. Routing is performed on the smaller size grid based on a modified shortest path technique. In the reverse process, the grid and subsequently all pre-routed paths are expanded. Additional routing of emergent nodes is performed at intermediate levels. Final routing concludes at the original level. When compared to single level routing, the algorithm dramatically improves execution time while preserving the quality of routing delays and routing lengths.