Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Layout design and verification
Layout design and verification
Routing in three-dimensional microelectronic structures
Routing in three-dimensional microelectronic structures
Chameleon: a new multi-layer channel router
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Near-optimal n-layer channel routing
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Performance of interconnection rip-up and reroute strategies
DAC '81 Proceedings of the 18th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
DAC '82 Proceedings of the 19th Design Automation Conference
Automated rip-up and reroute techniques
DAC '82 Proceedings of the 19th Design Automation Conference
Gravity: Fast placement for 3-D VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interconnect delay minimization through interlayer via placement in 3-D ICs
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Timing-driven via placement heuristics for three-dimensional ICs
Integration, the VLSI Journal
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Routability checking for three-dimensional architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multilevel routing for 3-dimensional circuits
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
| Hi-index | 14.98 |
As the very large scale integration (VLSI) technology approaches its fundamental scaling limit at about 0.2 μm, it is reasonable to consider three-dimensional (3-D) integration to enhance packing density and speed performance. With additional functional units packed into one chip in a 3-D space, computer-aided design (CAD) tools are demanded to ease the complicated design work. This paper presents a 100% completion achievable routing methodology. The routing methodology is based on the two-dimensional (2D) channel routing methodology; thus, it is called a 3-D channel routing methodology. With the routing methodology, a 3-D routing problem is decomposed into two 2D routing subproblems: intra-layer routing that interconnects terminals on the same layer, which can be done by using a 2-D channel router, and inter-layer routing that interconnects terminals on different layers. The inter-layer routing problem is transformed into a 2-D channel routing problem and the transformation is made in some 3-D channels. Detailed discussions are given for the 3-D to 2-D transformation. Optimization of the transformation is shown to be NP-complete. Thus, simulated annealing is used to optimize the transformation