DAC '76 Proceedings of the 13th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A new efficient approach to multilayer channel routing problem
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A multi-layer channel router with new style of over-the-cell routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Routing in a Three-Dimensional Chip
IEEE Transactions on Computers
Highlight of VLSI at research Berkeley
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
A gridless multi-layer router for standard cell circuits using CTM cells
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Channel routing in Manhattan-diagonal model
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
On the k-layer planar subset and via minimization problems
EURO-DAC '90 Proceedings of the conference on European design automation
Interconnect design methods for memory design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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New techniques for routing general multi-layer channels are introduced. These techniques can handle a variety of technology constraints. For example, linewidth and line-to-line spacing can be specified independently for each layer, and contact stacking can be allowed or forbidden. These techniques have been implemented in a new multi-layer channel router called Chameleon. Chameleon consists of two stages: a partitioner and a detailed router. The partitioner divides the problem into two and three-layer subproblems such that global channel area is minimized. The detailed router then implements the connections using generalizations of the algorithms used in YACR2. In particular a three-dimensional maze router is used which guarantees that any problem can be routed even when cyclic constraints are present. Chameleon produces optimal results on a wide range of industrial and academic examples for any number of layers and pitch combinations.