General purpose router

Authors:
R. J. Enbody;H. C. Du
Affiliations:
Dept. of Computer Science, University of Minnesota, Minneapolis, MN;Dept. of Computer Science, University of Minnesota, Minneapolis, MN
Venue:
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Year:
1987

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Abstract

Numerous solutions to the problem of detailed routing of wires on a chip have been proposed for two routing layers but few are general enough to also handle switchboxes, more than two layers, variable channel widths, or multiple-layer problems with stacked terminals (3-D routing) without extensive modifications. We propose a different routing approach that not only can solve the two layer problem but the other problems as well. The inherent parallelism of the approach lead to a coarse-grained parallel algorithm.