The interconnection problem - a tutorial
DAC '73 Proceedings of the 10th Design Automation Workshop
An analytic technique for router comparison
DAC '76 Proceedings of the 13th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
Some theoretical aspects of algorithmic routing
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '79 Proceedings of the 16th Design Automation Conference
An interactive routing program with On-line clean-up of sketched routes
DAC '79 Proceedings of the 16th Design Automation Conference
Fundamentals of Applied Probability Theory
Fundamentals of Applied Probability Theory
A distributed routing system for multilayer SOG
EURO-DAC '92 Proceedings of the conference on European design automation
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Routing in a Three-Dimensional Chip
IEEE Transactions on Computers
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Tolerating operational faults in cluster-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
The Journal of Supercomputing
Automated rip-up and reroute techniques
DAC '82 Proceedings of the 19th Design Automation Conference
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
A multilevel congestion-based global router
VLSI Design
A route system based on ant colony for coarse-grain reconfigurable architecture
ICNC'06 Proceedings of the Second international conference on Advances in Natural Computation - Volume Part II
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Rip-up and reroute strategies can be applied following use of conventional wiring algorithms to calculate paths for residual connections failed by preceding techniques. The removal of blocking wire to allow new path runs inevitably introduces new (reroute) wiring requirements. In this paper we address the performance implications of various rates of success experienced while attempting reroutes. Using statistical approaches, we develop formulas which allow calculation of expected completion rate and computational effort for several types of rip-up and reroute algorithms. It is found that a basic router having modest completion rate behavior can be used to achieve surprisingly high completion rates, with rip-up strategies.