Routability checking for three-dimensional architectures

Authors:
William N. N. Hung;Xiaoyu Song;Timothy Kam;Lerong Cheng;Guowu Yang
Affiliations:
Synplicity Inc., Sunnyvale, CA and Portland State University, OR;Portland State University, OR;Intel Corporation, Hillsboro, OR;Portland State University, OR;Portland State University, OR
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

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Abstract

We present a novel symbolic routability checking approach for three-dimensional interconnect layout. The model considered is a general architecture that can fit into different applications, such as ASIC, multi-chip modules, field-programmable gate arrays, and reconfigurable computing architectures. The method can incrementally incorporate additional constraints driven by timing, performance, and design. We used the latest satisfiability solver to validate the effectiveness of our approach. The experimental results demonstrate the encouraging performance on difficult routing benchmarks.