Coloring heuristics for register allocation
PLDI '89 Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation
The priority-based coloring approach to register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
On the parallel complexity of discrete relaxation in constraint satisfaction networks
Artificial Intelligence
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
ECAI '92 Proceedings of the 10th European conference on Artificial intelligence
Exact coloring of real-life graphs is easy
DAC '97 Proceedings of the 34th annual Design Automation Conference
Efficient coloring of a large spectrum of graphs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Circuit clustering using graph coloring
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Fast Approximation Algorithms on Maxcut, k-Coloring, and k-Color Ordering for VLSI Applications
IEEE Transactions on Computers
Graph coloring algorithms for fast evaluation of Curtis decompositions
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Register allocation by priority-based coloring
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing
Proceedings of the 2002 international symposium on Physical design
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Unifying SAT-based and Graph-based Planning
IJCAI '99 Proceedings of the Sixteenth International Joint Conference on Artificial Intelligence
SAT-Encodings, Search Space Structure, and Local Search Performance
IJCAI '99 Proceedings of the Sixteenth International Joint Conference on Artificial Intelligence
IJCAI '99 Proceedings of the Sixteenth International Joint Conference on Artificial Intelligence
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Accelerated SAT-based Scheduling of Control/Data Flow Graphs
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
On the Relation between SAT and BDDs for Equivalence Checking
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Constraint Processing
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Board-level multiterminal net assignment for the partial cross-bar architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints
IEEE Transactions on Computers
A generalized algorithm for graph-coloring register allocation
Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
SAT-Based Techniques in System Synthesis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Segmented channel routability via satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Comparative Study of Strategies for Formal Verification of High-Level Processors
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Partition-based logical reasoning for first-order and propositional theories
Artificial Intelligence - Special volume on reformulation
Guiding CNF-SAT search via efficient constraint partitioning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Comparison of schemes for encoding unobservability in translation to SAT
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Another look at graph coloring via propositional satisfiability
Discrete Applied Mathematics
Automatic SAT-compilation of planning problems
IJCAI'97 Proceedings of the Fifteenth international joint conference on Artifical intelligence - Volume 2
Breaking instance-independent symmetries in exact graph coloring
Journal of Artificial Intelligence Research
Understanding the power of clause learning
IJCAI'03 Proceedings of the 18th international joint conference on Artificial intelligence
Solving non-Boolean satisfiability problems with stochastic local search
IJCAI'01 Proceedings of the 17th international joint conference on Artificial intelligence - Volume 1
Compact propositional encodings of first-order theories
IJCAI'05 Proceedings of the 19th international joint conference on Artificial intelligence
Routability checking for three-dimensional architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variable ordering for efficient SAT search by analyzing constraint-variable dependencies
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Comparison of Boolean satisfiability encodings on FPGA detailed routing problems
Proceedings of the conference on Design, automation and test in Europe
Exact DFA identification using SAT solvers
ICGI'10 Proceedings of the 10th international colloquium conference on Grammatical inference: theoretical results and applications
Automatic formal verification of multithreaded pipelined microprocessors
Proceedings of the International Conference on Computer-Aided Design
Programming for modular reconfigurable robots
Programming and Computing Software
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Many important EDA problems can be formulated as graph coloring, which is a class of the Constraint Satisfaction Problem (CSP). This paper makes three contributions. First, we define new encodings for representing CSPs as equivalent Boolean Satisfiability (SAT) problems: 1) a generalization of the log encoding by using ITE trees to select the domain values of a CSP variable, so that only conflict clauses are required; and 2) a simplified direct encoding, derived from the direct encoding (where each domain value of a CSP variable is indexed by a unique Boolean variable) by omitting one of the Boolean variables and the at-least-one clause. Second, we propose the use of hierarchical encodings that combine several simple encodings to index the domain values of CSP variables, in order to produce SAT formulas that depend on fewer Boolean variables and are easier to solve. Third, we study schemes for static ordering of the Boolean variables in a Conjunctive Normal Form (CNF) representation of a CSP, based on the structure of the CSP graph, such that the resulting variable order is used for the decisions made by a SAT solver when evaluating the CNF. We compare 12 previously known SAT encodings for CSP with the two new encodings, as well as with 10 hybrid encodings. With symmetry-breaking constraints enforced, static variable ordering produced up to 2 orders of magnitude speedup. Additionally exploiting hierarchical encodings resulted in another order of magnitude speedup.