Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On the parallel complexity of discrete relaxation in constraint satisfaction networks
Artificial Intelligence
Generating hard satisfiability problems
Artificial Intelligence - Special volume on frontiers in problem solving: phase transitions and complexity
FPGA routing and routability estimation via Boolean satisfiability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing
Proceedings of the 2002 international symposium on Physical design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
SAT-Encodings, Search Space Structure, and Local Search Performance
IJCAI '99 Proceedings of the Sixteenth International Joint Conference on Artificial Intelligence
IJCAI '99 Proceedings of the Sixteenth International Joint Conference on Artificial Intelligence
Constraint Processing
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Board-level multiterminal net assignment for the partial cross-bar architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints
IEEE Transactions on Computers
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Segmented channel routability via satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Comparative Study of Strategies for Formal Verification of High-Level Processors
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Comparison of schemes for encoding unobservability in translation to SAT
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Exploiting hierarchy and structure to efficiently solve graph coloring as SAT
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Another look at graph coloring via propositional satisfiability
Discrete Applied Mathematics
Breaking instance-independent symmetries in exact graph coloring
Journal of Artificial Intelligence Research
Solving non-Boolean satisfiability problems with stochastic local search
IJCAI'01 Proceedings of the 17th international joint conference on Artificial intelligence - Volume 1
Routability checking for three-dimensional architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new FPGA detailed routing approach via search-based Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We compare 12 new encodings for representing of FPGA detailed routing problems as equivalent Boolean Satisfiability (SAT) problems against the only 2 previously used encodings. We also consider two symmetry-breaking heuristics. Compared to other methods for FPGA detailed routing, SAT-based approaches have the advantage that they can prove the unroutability of a global routing for a particular number of tracks per channel, and that they consider all nets simultaneously. The experiments were run on the standard MCNC benchmarks. The combination of one new encoding with a new symmetry-breaking heuristic resulted in speedup of 3 orders of magnitude or 1,139x of the total execution time on the collection of benchmarks, when proving the unroutability of FPGA global routings. The maximum obtained speedup was 9,499x on an individual benchmark. On the other hand, most of the encodings had comparable and very efficient performance when finding solutions for configurations that were routable. The availability of many SAT encodings, that can each be combined with various symmetry-breaking heuristics, opens the possibility to design portfolios of parallel strategies---each a combination of a SAT encoding and a symmetry-breaking heuristic---that can be run in parallel on different cores of a multicore CPU in order to reduce the solution time, with the rest of the runs terminated as soon as one of them returns an answer. We found that a portfolio of three particular parallel strategies produced additional speedup of more than 2x.