Field-programmable gate arrays
Field-programmable gate arrays
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
A performance and routablity driven router for FPGAs considering path delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Performance-oriented placement and routing for field-programmable gate arrays
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
A machine program for theorem-proving
Communications of the ACM
An exact algorithm for solving difficult detailed routing problems
Proceedings of the 2001 international symposium on Physical design
A comparative study of two Boolean formulations of FPGA detailed routing constraints
Proceedings of the 2001 international symposium on Physical design
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
Integrating Equivalency Reasoning into Davis-Putnam Procedure
Proceedings of the Seventeenth National Conference on Artificial Intelligence and Twelfth Conference on Innovative Applications of Artificial Intelligence
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Architectures and algorithms for field-programmable gate arrays with embedded memory
Architectures and algorithms for field-programmable gate arrays with embedded memory
Using CSP look-back techniques to solve real-world SAT instances
AAAI'97/IAAI'97 Proceedings of the fourteenth national conference on artificial intelligence and ninth conference on Innovative applications of artificial intelligence
New performance-driven FPGA routing algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new FPGA detailed routing approach via search-based Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Propositional Satisfiability and Constraint Programming: A comparative survey
ACM Computing Surveys (CSUR)
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Exploiting hierarchy and structure to efficiently solve graph coloring as SAT
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Comparison of Boolean satisfiability encodings on FPGA detailed routing problems
Proceedings of the conference on Design, automation and test in Europe
Layout generator for transistor-level high-density regular circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient conflict analysis for finding all satisfying assignments of a boolean circuit
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
A constraint satisfaction approach for programmable logic detailed placement
SAT'13 Proceedings of the 16th international conference on Theory and Applications of Satisfiability Testing
| Hi-index | 14.98 |
Abstract--This paper presents empirical analyses of two Boolean Satisfiability (SAT) formulations of FPGA (Field Programmable Gate Array) detailed routing constraints. Boolean SAT-based routing transforms a routing problem into a Boolean SAT instance by rendering geometric routing constraints as an atomic Boolean function. The generated Boolean function is satisfiable if and only if the corresponding routing is possible. Two different Boolean SAT-based routing models are analyzed: the track-based and the route-based routing constraint model. The track-based routing model transforms a routing task into a net-to-track assignment problem, whereas the route-based routing model reduces it into a routability-checking problem with explicitly enumerated set of detailed routes for nets. In both models, routing constraints are represented as CNF Boolean Satisfiability clauses. Through comparative experiments, we demonstrate that the route-based formulation yields an easier-to-evaluate and more scalable routability Boolean function than the track-based method. This is empirical evidence that a smart/efficient Boolean formulation can achieve significant performance improvement in real-world applications.