Layout generator for transistor-level high-density regular circuits

Authors:
Yi-Wei Lin;Malgorzata Marek-Sadowska;Wojciech P. Maly
Affiliations:
Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA;Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA;Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2010

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Abstract

In this paper, we describe an automatic place and route strategy for a high-density, super-regular, double-gate, transistor-array-based layout. Interconnects on all metal layers are strictly parallel and can be manufactured by an optical proximity correction free process. Our objective is to achieve a circuit layout area equal to the transistor footprint. Such layout constraints limit routing flexibility and render traditional approaches impractical. Our tools automatically generate circuits with several tens of transistors. Experimental results demonstrate both the efficiency of the proposed algorithms and the high quality of the layouts produced.