IC design in high-cost nanometer-technologies era
Proceedings of the 38th annual Design Automation Conference
Heterogeneous Programmable Logic Block Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design methodology for IC manufacturability based on regular logic-bricks
Proceedings of the 42nd annual Design Automation Conference
Transistor-level layout of high-density regular circuits
Proceedings of the 2009 international symposium on Physical design
Performance study of VeSFET-based, high-density regular circuits
Proceedings of the 19th international symposium on Physical design
Layout generator for transistor-level high-density regular circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries
Proceedings of the 48th Design Automation Conference
Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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Advancements in IC manufacturing technologies allow for building very large devices with billions of transistors and with complex interactions between them encapsulated in a huge number of design rules. To ease designers' efforts in dealing with electrical and manufacturing problems, regular layout style seems to be a viable option. In this paper we analyze regular layouts in an IC manufacturability context and define their desired properties. We introduce the OPC-free IC design methodology and study properties of cells designed for this layout style that have various degrees of regularity.