An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Potential Slack Budgeting with Clock Skew Optimization
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Design methodology for IC manufacturability based on regular logic-bricks
Proceedings of the 42nd annual Design Automation Conference
A metal and via maskset programmable VLSI design methodology using PLAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
OPC-free and minimally irregular IC design style
Proceedings of the 44th annual Design Automation Conference
Optimal Layout of CMOS Functional Arrays
IEEE Transactions on Computers
Transistor-level layout of high-density regular circuits
Proceedings of the 2009 international symposium on Physical design
MaizeRouter: Engineering an Effective Global Router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we study circuits implemented using high-density arrays composed of Vertical Slit Field Effect Transistors. This layout style could dramatically increase transistor density and therefore reduce fabrication cost. However, its geometrical restrictions, imposed by the super-regular transistor arrangement and strictly parallel metal tracks pose new design challenges. Our experiments reveal that very dense cell-level interconnect pattern may be responsible for unnecessary 15% increase of the circuit-level, critical path delays. We demonstrate that these extra delays can be avoided by constructing appropriate cell interconnect layouts and by more flexible usage of available metal layers for intra-cell routing. To balance the performance and metal layer usage, we propose a linear programming-based technique for critical net re-routing.