Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
New efficient algorithms for computing effective capacitance
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A crosstalk-aware timing-driven router for FPGAs
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Method to Estimate Slew and Delay in Coupled Digital Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Performance study of VeSFET-based, high-density regular circuits
Proceedings of the 19th international symposium on Physical design
| Hi-index | 0.00 |
The impact of interconnect coupling, in the form of delay and crosstalk, in deep submicron integrated circuit design is increasing. In many cases, especially in routing, the coupling capacitance, Cc, between adjacent lines is decoupled and replaced by 2Cc connected to ground for fast worst-case delay estimation. This is based on the assumption that worst-case delay occurs when two adjacent lines switch simultaneously in opposite directions so that the voltage change across the coupling capacitance is twice that when only one line is switching. Similarly, when two adjacent lines switch simultaneously in the same direction, the coupling capacitance is put to zero based on the fact that the voltage difference across it is zero. However, we show that by replacing the coupling capacitance Cc with a grounded capacitance of 2Cc (or by zero) when signals switch simultaneously in opposite (or same) directions may overestimate or even underestimate the actual delay. The variable strengths of the drivers driving the coupled lines bring in an additional level of complexity to the delay estimation when coupling exists. In this paper, we derive a simple analytical model that takes the effect of different driver strengths into account, to accurately estimate the delay and crosstalk of two coupled interconnect lines switching simultaneously. This approach also gives the exact values of the multiplicants that Cc should be multiplied with, if the lines are to be decoupled, for both worst-case and best-case delay computation; that is when the signals switch in opposite direction and when they switch in the same direction.