Exact combinatorial optimization methods for physical design of regular logic bricks
Proceedings of the 44th annual Design Automation Conference
OPC-free and minimally irregular IC design style
Proceedings of the 44th annual Design Automation Conference
Transistor-level layout of high-density regular circuits
Proceedings of the 2009 international symposium on Physical design
Lithography options for the 32 nm half pitch node and beyond
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Standard cell routing via boolean satisfiability
Proceedings of the 49th Annual Design Automation Conference
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In this work we propose a regular layout fabric practical for industrial random logic design and present cell synthesis algorithms specialized to this fabric. We show results on an industrial test-case where physical synthesis onto a library of extremely regular cells results in only 7% increase in leakage in comparison to traditional standard cells. We also show that using this fabric based cell synthesis system allows better overall area by allowing more upper layer routing. We achieve a 4% routable die size reduction by simultaneous cell synthesis and custom M1 routing.