Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Field-programmable gate arrays
Field-programmable gate arrays
On routability prediction for field-programmable gate arrays
DAC '93 Proceedings of the 30th international Design Automation Conference
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
A performance and routablity driven router for FPGAs considering path delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Performance-oriented placement and routing for field-programmable gate arrays
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A fast routability-driven router for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
FPGA routing and routability estimation via Boolean satisfiability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
A class of min-cut placement algorithms
DAC '77 Proceedings of the 14th Design Automation Conference
Architectures and algorithms for field-programmable gate arrays with embedded memory
Architectures and algorithms for field-programmable gate arrays with embedded memory
New performance-driven FPGA routing algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven simultaneous placement and routing for FPGA's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2001 international symposium on Physical design
Board-level multiterminal net assignment
Proceedings of the 12th ACM Great Lakes symposium on VLSI
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing
Proceedings of the 2002 international symposium on Physical design
Solving difficult SAT instances in the presence of symmetry
Proceedings of the 39th annual Design Automation Conference
Satometer:: how much have we searched?
Proceedings of the 39th annual Design Automation Conference
Faster SAT and smaller BDDs via common function structure
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Robust SAT-Based Search Algorithm for Leakage Power Reduction
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
FORCE: a fast and easy-to-implement variable-ordering heuristic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Generic ILP versus specialized 0-1 ILP: an update
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Shatter: efficient symmetry-breaking for boolean satisfiability
Proceedings of the 40th annual Design Automation Conference
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints
IEEE Transactions on Computers
AMUSE: a minimally-unsatisfiable subformula extractor
Proceedings of the 41st annual Design Automation Conference
ShatterPB: symmetry-breaking for pseudo-Boolean formulas
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Segmented channel routability via satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
GridSAT: A Chaff-based Distributed SAT Solver for the Grid
Proceedings of the 2003 ACM/IEEE conference on Supercomputing
Dynamic symmetry-breaking for improved Boolean optimization
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient Symmetry Breaking for Boolean Satisfiability
IEEE Transactions on Computers
GridSAT: a system for solving satisfiability problems using a computational grid
Parallel Computing - Optimization on grids - Optimization for grids
Symmetry breaking for pseudo-Boolean formulas
Journal of Experimental Algorithmics (JEA)
Using SAT-based techniques in power estimation
Microelectronics Journal
Solution and Optimization of Systems of Pseudo-Boolean Constraints
IEEE Transactions on Computers
Sidewinder: a scalable ILP-based router
Proceedings of the 2008 international workshop on System level interconnect prediction
Efficient symmetry breaking for boolean satisfiability
IJCAI'03 Proceedings of the 18th international joint conference on Artificial intelligence
PN code acquisition using Boolean satisfiability techniques
WCNC'09 Proceedings of the 2009 IEEE conference on Wireless Communications & Networking Conference
Finding unsatisfiable subformulas with stochastic method
IDEAL'07 Proceedings of the 8th international conference on Intelligent data engineering and automated learning
A heuristic local search algorithm for unsatisfiable cores extraction
ICCSA'07 Proceedings of the 2007 international conference on Computational science and its applications - Volume Part III
Dynamic symmetry-breaking for Boolean satisfiability
Annals of Mathematics and Artificial Intelligence
Automatically exploiting symmetries in constraint programming
CSCLP'04 Proceedings of the 2004 joint ERCIM/CoLOGNET international conference on Recent Advances in Constraints
| Hi-index | 0.01 |
A Boolean-based router expresses the routing constraints as a Bool冒ean function which is satisfiable if and only if the layout is routable. Compared to traditional routers, Boolean-based routers offer two unique features: (1) simultaneous embedding of all nets regardless of net ordering, and (2) ability to demonstrate routing infeasibility by proving the unsatisfiability of the generated routing constraint Boolean function. In this paper, we introduce a new Boolean-based FPGA detailed routing formulation that yields an easy-to-evaluate and more scalable routability Boolean function than the previous methods. The routability constraints are expressed in terms of a set of route variables each of which designating a specific detailed route for a given net. Experimental results clearly show the superi冒ority of this formulation over an earlier formulation that expressed the constraints in terms of track variables.