A comparative study of two Boolean formulations of FPGA detailed routing constraints
Proceedings of the 2001 international symposium on Physical design
Combinatorial routing analysis and design of universal switch blocks
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
On optimum switch box designs for 2-D FPGAs
Proceedings of the 38th annual Design Automation Conference
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
General models for optimum arbitrary-dimension FPGA switch box designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Reduction design for generic universal switch blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
General Models and a Reduction Design Technique for FPGA Switch Box Designs
IEEE Transactions on Computers
On Optimum Designs of Universal Switch Blocks
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints
IEEE Transactions on Computers
On improving FPGA routability applying multi-level switch boxes
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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In this paper, the routing problem for two-dimensional (2-D) field programmable gate arrays of a Xilinx-like architecture is studied. We first propose an efficient one-step router that makes use of the main characteristics of the architecture. Then we propose an improved approach of coupling two greedy heuristics designed to avoid an undesired decaying effect, a dramatically degenerated router performance on the near completion stages. This phenomenon is commonly observed on results produced by the conventional deterministic routing strategies using a single optimization cost function. Consequently, our results are significantly improved on both the number of routing tracks and routing segments by just applying low-complexity algorithms. On the tested MCNC and industrial benchmarks, the total number of tracks used by the best known two-step global/detailed router is 28% more than that used by our proposed method