On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A performance and routablity driven router for FPGAs considering path delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
New performance-driven FPGA routing algorithms
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the optimal four-way switch box routing structures of FPGA greedy routing architectures
Integration, the VLSI Journal
Graph Theory With Applications
Graph Theory With Applications
Graph based analysis of 2-D FPGA routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinatorial routing analysis and design of universal switch blocks
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
On optimum switch box designs for 2-D FPGAs
Proceedings of the 38th annual Design Automation Conference
Comment on Generic Universal Switch Blocks
IEEE Transactions on Computers
Reduction design for generic universal switch blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On Optimum Designs of Universal Switch Blocks
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
The exact channel density and compound design for generic universal switch blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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An FPGA switch box is said to be hyper-universal if it is routable for all possible surrounding multi-pin net topologies satisfying the routing resource constraints. It is desirable to design hyper-universal switch boxes with the minimum number of switches. A previous work, Universal Switch Module, considered such a design problem concerning 2-pin net routings around a single FPGA switch box. However, as most nets are multi-pin nets in practice, it is imperative to study the problem that involves multi-pin nets. In this paper, we provide a new view of global routings and formulate the most general κ-sided switch box design problem into an optimum κ-partite graph design problem. Applying a powerful decomposition theorem of global routings, we prove that, for a fixed κ, the number of switches in an optimum κ-sided switch box with W terminals on each side is O (W), by constructing some hyper-universal switch boxes with O(W) switches. Furthermore, we obtain optimum, hyper-universal 2-sided and 3-sided switch boxes, and propose hyper-universal 4-sided switch boxes with less than 6.7W switches, which is very close to the lower bound 6W obtained for pure 2-pin net models in [5].