PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
An FPGA architecture with enhanced datapath functionality
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Placement and Routing in 3D Integrated Circuits
IEEE Design & Test
Performance benefits of monolithically stacked 3D-FPGA
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Design tools for 3-D integrated circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Designing a 3-D FPGA: switch box architecture and thermal issues
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
Three Dimensional System Integration: IC Stacking Process and Design
Three Dimensional System Integration: IC Stacking Process and Design
On Supporting Rapid Thermal Analysis
IEEE Computer Architecture Letters
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Interlaced switch boxes placement for three-dimensional FPGA architecture design
International Journal of Circuit Theory and Applications
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The interconnection structures in FPGA devices increasingly contribute more to the delay, power consumption and area overhead. The demand for even higher clock frequencies makes this problem even more important. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moores momentum and fuel the next wave of consumer electronics products. However, the benefits of such a new integration paradigm have not been sufficiently explored yet. In this paper, a novel 3-D architecture, as well as the software supporting tools for exploring and evaluating application implementation, are introduced. More specifically, by assigning to different layers logic and I/O resources, we achieve mentionable wire-length reduction. Experimental results prove the effectiveness of such a selection, since target architectures outperform the conventional 2-D FPGAs.