Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
An FPGA architecture with enhanced datapath functionality
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Wiring requirement and three-dimensional integration technology for field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Technology, performance, and computer-aided design of three-dimensional integrated circuits
Proceedings of the 2004 international symposium on Physical design
Placement and Routing in 3D Integrated Circuits
IEEE Design & Test
Performance benefits of monolithically stacked 3D-FPGA
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Multiobjective hypergraph-partitioning algorithms for cut and maximum subdomain-degree minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A framework for architecture-level exploration of 3-D FPGA platforms
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A novel 3-D FPGA architecture targeting communication intensive applications
Journal of Systems Architecture: the EUROMICRO Journal
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Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencies and logic densities is also important for the Field-Programmable Gate Array (FPGA) paradigm. Three-dimensional (3-D) integration can alleviate such performance limitations by accommodating a number of additional silicon layers. However, the benefits of 3-D integration have yet to be sufficiently investigated. In this paper, we propose a software-supported methodology to explore and evaluate 3-D FPGAs fabricated with alternative technologies. Based on the evaluation results, the proposed FPGA device improves speed and energy dissipation by approximately 38% and 26%, respectively, as compared to 2-D FPGAs. Furthermore, these gains are achieved in addition to reducing the interlayer connections, as compared to existing design approaches, leading to cheaper and more reliable architectures.