A framework for architecture-level exploration of 3-D FPGA platforms

Authors:
Harry Sidiropoulos;Kostas Siozios;Dimitrios Soudris
Affiliations:
School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece;School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece;School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece
Venue:
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Year:
2011

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Abstract

Interconnection structures in FPGAs increasingly contribute more to the delay and power consumption. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next wave of consumer electronics products. However, the benefits of such a technology have not been sufficiently explored yet. This paper introduces a novel 3-D FPGA, where logic, memory and I/O resources are assigned to different layers. Experimental results prove the efficiency of our architecture for a wide range of application domains, since we achieve average performance improvement and power saving of 30% and 10%, respectively.