The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
System-level performance evaluation of three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Microstructure examination of copper wafer bonding
Journal of Electronic Materials - Special issue on advances in materials science of IC interconnects and packaging
Wiring requirement and three-dimensional integration technology for field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
DAC '84 Proceedings of the 21st Design Automation Conference
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Design tools for 3-D integrated circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Three-Dimensional Cache Design Exploration Using 3DCacti
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
3D Chip Stack Technology Using Through-Chip Interconnects
IEEE Design & Test
Optimal topology exploration for application-specific 3D architectures
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Integrating dynamic thermal via planning with 3D floorplanning algorithm
Proceedings of the 2006 international symposium on Physical design
Thermal analysis of a 3D die-stacked high-performance microprocessor
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
How does partitioning matter for 3D floorplanning?
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Dynamic instruction schedulers in a 3-dimensional integration technology
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
2D data locality: definition, abstraction, and application
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Low-power clock distribution in a multilayer core 3d microprocessor
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A modular 3d processor for flexible product design and technology migration
Proceedings of the 5th conference on Computing frontiers
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
3D-Stacked Memory Architectures for Multi-core Processors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design space exploration for 3-D cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Maximizing the functional yield of wafer-to-wafer 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SOC'09 Proceedings of the 11th international conference on System-on-chip
The impact of liquid cooling on 3D multi-core processors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
Vertical interconnects squeezing in symmetric 3D mesh network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture
Journal of Computer and System Sciences
High-speed dynamic TDMA arbiter for inter-layer communications in 3-D network-on-chip
Journal of High Speed Networks
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We present an overview of a new monolithic fabrication technology known as three-dimensional integration. 3D integration refers to any process by which multiple conventional device layers may be stacked and electrically interconnected. By combining state-of-the-art single-wafer integration with a high-density inter-wafer interconnect, our 3D integration process is capable of providing improved circuit performance in terms of metrics such as wire length, area, timing, and energy consumption. In this paper, we will discuss the overall 3D integration process flow, as well as specific technological challenges and the issues they present to circuit designers. We will also describe how these issues may be tackled during the placement, routing, and layout stages of physical design. Finally, we will present some performance results that may be obtained by integrating circuits in three dimensions.