Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
The Alpha 21264 Microprocessor
IEEE Micro
Technology, performance, and computer-aided design of three-dimensional integrated circuits
Proceedings of the 2004 international symposium on Physical design
A sliding window scheme for accurate clock mesh analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Proceedings of the 43rd annual Design Automation Conference
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Architecting Microprocessor Components in 3D Design Space
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Clock tree synthesis with pre-bond testability for 3D stacked IC designs
Proceedings of the 47th Design Automation Conference
Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock Tree synthesis for TSV-based 3D IC designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fault-tolerant 3D clock network
Proceedings of the 48th Design Automation Conference
Effect of process variations in 3D global clock distribution networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Clock distribution networks are extremely critical from a performance and power standpoint. They account for about 20-30% of the total power dissipated in current generation microprocessors. Many three-dimensional (3D) schemes propose to reduce interconnect length to improve performance and decrease power consumption. In this paper we propose a clock distribution network for a 3D multilayer core microprocessor. The 3D microprocessor floor plan has a single core folded onto multiple layers. A separate layer for the clock distribution network is proposed in the 3D microprocessor. This arrangement of a 3D chip stack reduces (a) power lost in long interconnects at block level and (b) in the clock distribution. Simulation results indicate a 15-20% power saving for this clock distribution scheme as compared to a 2D structure. A methodology for turning off the global clock grid along with the logic for an entire layer in a 3D stack is also proposed. Simulation results indicate an additional 8-10% savings in power with minimal impact on the critical parameters of the clock grid.