Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal wire and transistor sizing for circuits with non-tree topology
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
SPRIM: structure-preserving reduced-order interconnect macromodeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Analyzing timing uncertainty in mesh-based clock architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A frequency-domain technique for statistical timing analysis of clock meshes
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Low-power clock distribution in a multilayer core 3d microprocessor
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A novel scheme to reduce short-circuit power in mesh-based clock architectures
Proceedings of the 21st annual symposium on Integrated circuits and system design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast symbolic computation approach to statistical analysis of mesh networks with multiple sources
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Meshworks: a comprehensive framework for optimized clock mesh network synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Proceedings of the International Conference on Computer-Aided Design
Crosslink insertion for variation-driven clock network construction
Proceedings of the great lakes symposium on VLSI
Decentralized and passive model order reduction of linear networks with massive ports
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Mesh architectures are used for distributing critical global signals on a chip such as clock and power/ground. The inherent redundancy created by loops present in the mesh smooths out undesirable variations between signal nodes spatially distributed over the chip. However, one outstanding problem with mesh architectures is the difficulty in analyzing them with sufficient accuracy. In this paper, we present a new sliding window-based scheme to analyze the latency in clock meshes. We show that for small meshes, our scheme comes within 1% of the SPICE simulation of the complete mesh with respect to clock latency. Our scheme is ideally suited for distributed- or grid-computing. We show large design instances where SPICE could not finish, whereas our scheme could complete the analysis in less than 2 hours.