Multi-GHz interconnect effects in microprocessors
Proceedings of the 2001 international symposium on Physical design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A sliding window scheme for accurate clock mesh analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design and Analysis of "Tree+Local Meshes" Clock Architecture
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Meshes are widely used for distributing clock in high performance designs. In the past, they were used exclusively for microprocessors, now they are being integrated into the ASIC design flow as well. A mesh has a much smaller skew and jitter, but the high power consumption limits its applicability. In this work, we address the high power consumption of mesh architectures. We propose a novel design for mesh buffers to minimize the short circuit current caused by the different arrival times of the clock signal at mesh buffer inputs. By reducing the short circuit current, we show that the mesh power consumption is reduced by up to 59% and skew by 22%.