Efficient linear circuit analysis by Pade´ approximation via the Lanczos process
EURO-DAC '94 Proceedings of the conference on European design automation
Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Zeros and passivity of Arnoldi-reduced-order models for interconnect networks
DAC '97 Proceedings of the 34th annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Lanczos-type method for multiple starting vectors
Mathematics of Computation
Krylov-subspace methods for reduced-order modeling in circuit simulation
Journal of Computational and Applied Mathematics - Special issue on numerical analysis 2000 Vol. III: linear algebra
Proceedings of the conference on Design, automation and test in Europe
Dissipative Systems Analysis and Control: Theory and Applications
Dissipative Systems Analysis and Control: Theory and Applications
Robust and passive model order reduction for circuits containing susceptance elements
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses
Proceedings of the conference on Design, automation and test in Europe
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Structure preserving reduction of frequency-dependent interconnect
Proceedings of the 42nd annual Design Automation Conference
Compact Reduced Order Modeling for Multiple-Port Interconnects
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An efficient method for terminal reduction of interconnect circuits considering delay variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A sliding window scheme for accurate clock mesh analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Model order reduction of linear networks with massive ports via frequency-dependent port packing
Proceedings of the 43rd annual Design Automation Conference
A fast block structure preserving model order reduction for inverse inductance circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
SBPOR: second-order balanced truncation for passive order reduction of RLC circuits
Proceedings of the 44th annual Design Automation Conference
An efficient terminal and model order reduction algorithm
Integration, the VLSI Journal
SPARE: a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction
Proceedings of the conference on Design, automation and test in Europe
Multiple block structure-preserving reduced order modeling of interconnect circuits
Integration, the VLSI Journal
Sparse and Passive Reduced-Order Interconnect Modeling by Eigenspace Method
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Efficient methods for large resistor networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SPARE: a scalable algorithm for passive, structure preserving, parameter-aware model order reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
PABTEC: passivity-preserving balanced truncation for electrical circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the efficient reduction of complete EM based parametric models
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient model reduction of interconnects via double gramians approximation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fast analysis of a large-scale inductive interconnect by block-structure-preserved macromodeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Structure preserving reduced-order modeling of linear periodic time-varying systems
Proceedings of the International Conference on Computer-Aided Design
Full-chip runtime error-tolerant thermal estimation and prediction for practical thermal management
Proceedings of the International Conference on Computer-Aided Design
Model order reduction of coupled circuit-device systems
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
Decentralized and passive model order reduction of linear networks with massive ports
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Runtime power estimator calibration for high-performance microprocessors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Electronic Testing: Theory and Applications
Mathematics and Computers in Simulation
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In recent years, order-reduction techniques based on Krylov subspaces have become the methods of choice for generating macromodels of large multi-port RLC circuits. A widely-used method of this type is PRIMA. Its main features are provably passive reduced-order models and a moment-matching property. On the other hand, PRIMA does not preserve other structures, such as reciprocity or the block structure of the circuit matrices, inherent to RLC circuits, which makes it harder to synthesize the PRIMA models as actual circuits. Moreover, the PRIMA models match only half as many moments as optimal, but non-passive, moment-matching techniques such as SyMPVL. In this paper, we propose the reduction technique SPRIM that overcomes these disadvantages of PRIMA. In particular, SPRIM generates provably passive and reciprocal macromodels of multi-port RLC circuits, and the SPRIM models match twice as many moments as the corresponding PRIMA models obtained with identical computational work. Numerical results are reported that illustrate the higher accuracy of SPRIM vs. PRIMA.