Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Exploiting the on-chip inductance in high-speed clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A local circuit topology for inductive parasitics
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Robust and passive model order reduction for circuits containing susceptance elements
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Iterative Methods for Sparse Linear Systems
Iterative Methods for Sparse Linear Systems
SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SPRIM: structure-preserving reduced-order interconnect macromodeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
Off-chip decoupling capacitor allocation for chip package co-design
Proceedings of the 44th annual Design Automation Conference
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
Preservation of passivity during RLC network reduction via split congruence transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An improved long distance treatment for mutual inductance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A provably passive and cost-efficient model for inductive interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Feasibility analysis of specialized PEEC solvers in comparison to SPICE-like solvers
Journal of Computational Electronics
A parallel and incremental extraction of variational capacitance with stochastic geometric moments
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Solution of PDEs-electrically coupled systems with electrical analogy
Integration, the VLSI Journal
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To efficiently analyze the large-scale interconnect dominant circuits with inductive couplings (mutual inductances), this paper introduces a new state matrix, called VNA, to stamp inverse-inductance elements by replacing inductive-branch current with flux. The state matrix under VNA is diagonal-dominant, sparse, and passive. To further explore the sparsity and hierarchy at the block level, a new matrix-stretching method is introduced to reorder coupled fluxes into a decoupled state matrix with a bordered block diagonal (BBD) structure. A corresponding block-structure-preserved model-order reduction, called BVOR, is developed to preserve the sparsity and hierarchy of the BBD matrix at the block level. This enables us to efficiently build and simulate the macromodel within a SPICE-like circuit simulator. Experiments show that our method achieves up to 7× faster modeling building time, up to 33× faster simulation time, and as much as 67× smaller waveform error compared to SAPOR [a second-order reduction based on nodal analysis (NA)] and PACT (a first-order 2 × 2 structured reduction based on modified NA).