Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Efficient inductance extraction via windowing
Proceedings of the conference on Design, automation and test in Europe
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Hierarchical interconnect circuit models
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Return-limited inductances: a practical approach to on-chip inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generation of equivalent circuits from physics-based device simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equipotential shells for efficient inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Vector potential equivalent circuit based on PEEC inversion
Proceedings of the 40th annual Design Automation Conference
CHIME: coupled hierarchical inductance model evaluation
Proceedings of the 41st annual Design Automation Conference
Frequency-dependent reluctance extraction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Partial reluctance based circuit simulation is efficient and stable
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast analysis of a large-scale inductive interconnect by block-structure-preserved macromodeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A novel circuit topology for inductive coupling between interconnecting wires is presented. The model is local, i.e., only coupling between neighboring wires is explicitly modeled. However, the topology accounts for long-range coupling by propagating the vector potential from one wire to the next. Examples of model calibration, both directly from layout and as model-order reduction of a given inductance matrix, are presented for simple wiring structures.