Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
SPIE: sparse partial inductance extraction
DAC '97 Proceedings of the 34th annual Design Automation Conference
Efficient inductance extraction via windowing
Proceedings of the conference on Design, automation and test in Europe
An efficient model for frequency-dependent on-chip inductance
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
On the efficacy of simplified 2D on-chip inductance models
Proceedings of the 39th annual Design Automation Conference
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A local circuit topology for inductive parasitics
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On-chip interconnect modeling by wire duplication
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Return-limited inductances: a practical approach to on-chip inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SCORE: SPICE COmpatible Reluctance Extraction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
CHIME: coupled hierarchical inductance model evaluation
Proceedings of the 41st annual Design Automation Conference
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A wideband hierarchical circuit reduction for massively coupled interconnects
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Partial reluctance based circuit simulation is efficient and stable
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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The geometry-integration based vector potential equivalent circuit (VPEC) was introduced to obtain a localized circuit model for inductive interconnects in [1]. In this paper, we show that the method in [1] is accurate only for the two body problem. We derive N-body VPEC models based on geometry integration and inversion of inductance matrix under the PEEC model, respectively. Both VPEC models are derived from first principles and are accurate compared to the full PEEC model. The resulting circuit matrix G can be analyzed directly by existing simulation tools such as SPICE, and the simulation time of VPEC model is 47X less than that for PEEC model for a bus structure with 256 wires. It is also passive and strictly diagonal dominant, which leads to efficient circuit sparsification methods such as numerical and geometry based sparsifications. Compared to the full PEEC model, the sparsified VPEC models are orders of magnitude faster and produce waveforms with very small error.