SPIE: sparse partial inductance extraction
DAC '97 Proceedings of the 34th annual Design Automation Conference
Efficient inductance extraction via windowing
Proceedings of the conference on Design, automation and test in Europe
The Designer's Guide to Spice and Spectre
The Designer's Guide to Spice and Spectre
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Realizable parasitic reduction using generalized Y-Δ transformation
Proceedings of the 40th annual Design Automation Conference
Realizable RLCK circuit crunching
Proceedings of the 40th annual Design Automation Conference
Vector potential equivalent circuit based on PEEC inversion
Proceedings of the 40th annual Design Automation Conference
A General S-Domain Hierarchical Network Reduction Algorithm
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of interconnect networks using complex frequency hopping (CFH)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vector potential equivalent circuit) model, which not only enables the passive sparsification but also gives correct low-frequency response, whereas the recent circuit reduction intrinsically has inaccurate value and low-frequency response due to nodal-susceptance formulation. Applying hierarchical circuit-reduction enhanced by multi-point expansions, we can obtain an accurate high-order impedance function to capture the high-frequency response. The impedance function is further enforced passivity by convex programming, and realized by a Foster's synthesis. Experiments show that our method is as accurate as PRIMA in high frequency range, but leads to a realized circuit model with up to 10X times less complexity and up to 8X smaller simulation time. In addition, under the same reduction ratio, its error margin is less than that for the time-constant based reduction in both time-domain and frequency-domain simulations.