Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Inductance 101: analysis and design issues
Proceedings of the 38th annual Design Automation Conference
Min/max on-chip inductance models and delay metrics
Proceedings of the 38th annual Design Automation Conference
A solenoidal basis method for efficient inductance extraction
Proceedings of the 39th annual Design Automation Conference
On the efficacy of simplified 2D on-chip inductance models
Proceedings of the 39th annual Design Automation Conference
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
INDUCTWISE: inductance-wise interconnect simulator and extractor
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A precorrected-FFT method for simulating on-chip inductance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On-chip interconnect modeling by wire duplication
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Vector potential equivalent circuit based on PEEC inversion
Proceedings of the 40th annual Design Automation Conference
Electrical Modeling of Integrated-Package Power and Ground Distributions
IEEE Design & Test
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
SCORE: SPICE COmpatible Reluctance Extraction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SPICE compatible circuit models for partial reluctance K
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Frequency-dependent reluctance extraction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Fast simulation of VLSI interconnects
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An efficient algorithm for 3-D reluctance extraction considering high frequency effect
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A wideband hierarchical circuit reduction for massively coupled interconnects
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
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Extracting the inductance of complex interconnect topologiesis a formidable task, and simulating the resulting dense partialinductance matrix is even more difficult. Furthermore, it is wellknown that simply discarding smallest terms to sparsify the inductancematrix can render the partial inductance matrix indefiniteand result in an unstable circuit model. In this paper, wedescribe a methodology for incrementally generating a sparsepartial inductance matrix based on using moments about s=0 todetermine when a sufficient number of mutual inductances havebeen captured. The minimally required mutual inductances areextracted for a provably stable model.