SPIE: sparse partial inductance extraction
DAC '97 Proceedings of the 34th annual Design Automation Conference
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Inductance 101: modeling and extraction
Proceedings of the 38th annual Design Automation Conference
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
INDUCTWISE: inductance-wise interconnect simulator and extractor
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Frequency-dependent reluctance extraction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Partial reluctance based circuit simulation is efficient and stable
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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As shown in literatures, partial reluctance based circuit analysis is efficient in capturing on-chip inductance effect, because the partial reluctance exhibits much better locality than partial inductance. However, most previous works on reluctance extraction did not take high frequency effect into account and were not efficient enough for 3-D complex structure. In this paper, a new reluctance extraction algorithm is proposed considering the high frequency effect. Numerical experiments demonstrate that our algorithm can handle complex 3-D interconnect structures while exhibiting high accuracy and a speed-up ratio of several tens to hundreds over FastHenry.