Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Modeling magnetic coupling for on-chip interconnect
Proceedings of the 38th annual Design Automation Conference
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A local circuit topology for inductive parasitics
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
INDUCTWISE: inductance-wise interconnect simulator and extractor
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On-chip interconnect modeling by wire duplication
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Vector potential equivalent circuit based on PEEC inversion
Proceedings of the 40th annual Design Automation Conference
An efficient algorithm for 3-D reluctance extraction considering high frequency effect
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
Partial reluctance K, the inversion of partial inductance L, is proposed by Devgan et al to capture the on-chip inductance effect [3]. Partial reluctance based circuit simulation is efficient and stable because it is believed that partial reluctance effect is local and partial reluctance matrix is positive definite, although it has not been proved or illustrated clearly. In this paper, we are going to prove that mutual partial reluctance effect between a completely shielded short conductor segment and a conductor segment outside the shield is zero, which implies that the partial reluctance effect is local. Also, an iterative cutting algorithm is proposed to guarantee the strong diagonal dominance of the partial reluctance matrix, which is a sufficient condition for the partial reluctance matrix to be positive definite. With these two characters of partial reluctance, the circuit simulation based on partial reluctance is efficient and stable.