Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
SPIE: sparse partial inductance extraction
DAC '97 Proceedings of the 34th annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
IC analyses including extracted inductance models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An efficient model for frequency-dependent on-chip inductance
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Inductance 101: analysis and design issues
Proceedings of the 38th annual Design Automation Conference
Min/max on-chip inductance models and delay metrics
Proceedings of the 38th annual Design Automation Conference
Built-in self-test for signal integrity
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Technology trends in power-grid-induced noise
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Estimation of the likelihood of capacitive coupling noise
Proceedings of the 39th annual Design Automation Conference
A solenoidal basis method for efficient inductance extraction
Proceedings of the 39th annual Design Automation Conference
On the efficacy of simplified 2D on-chip inductance models
Proceedings of the 39th annual Design Automation Conference
Worst case clock skew under power supply variations
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows
Analog Integrated Circuits and Signal Processing
Full-chip, three-dimensional, shapes-based RLC extraction
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
Impact of Technology in Power-Grid-Induced Noise
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
INDUCTWISE: inductance-wise interconnect simulator and extractor
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A precorrected-FFT method for simulating on-chip inductance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Estimation of signal arrival times in the presence of delay noise
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On-chip power supply network optimization using multigrid-based technique
Proceedings of the 40th annual Design Automation Conference
SCORE: SPICE COmpatible Reluctance Extraction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Frequency-dependent reluctance extraction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Accurate capture of timing parameters in inductively-coupled on-chip interconnects
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Analog Integrated Circuits and Signal Processing
Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling
Analog Integrated Circuits and Signal Processing
An efficient algorithm for 3-D reluctance extraction considering high frequency effect
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A metric for analyzing effective on-chip inductive coupling
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A new RLC buffer insertion algorithm
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With operating frequencies approaching the gigahertz range, inductance is becoming an increasingly important consideration in the design and analysis of on-chip interconnect. We present an accurate technique for modeling and analyzing the effects of parasitic inductance on power grid noise, signal delay and crosstalk. We propose a detailed circuit model composed of interconnect resistance, inductance and distributed capacitance, device decoupling capacitances, quiescent activity in the grid, pad locations, and pad/package inductance which accurately determines current distribution and, hence, on-chip inductive effects, and proves superior to the traditional simplified loop inductance approach. The model uses partial inductances, computed using an analytical formula for a pair of parallel rectangular conductors spaced in any relative position. We present experimental results, obtained from simulations of industrial circuits, that show the importance of various model components while analyzing on-chip inductance. We also propose a simple sparsification technique to handle large, dense partial inductance matrices.