On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Proceedings of the 2002 international symposium on Physical design
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Due to technology scaling, the trend for integrated circuits is towards higher power dissipation, higher frequency and lower supply voltages. As a result, the power supply current delivered through the on-chip power grid is increasing dramatically, which is recognized in the International Technology Roadmap for Semiconductors as a difficult challenge. Early power grid design and the addition of decoupling capacitance have become crucially important to control power-grid-induced noise. We show analytical relationships and simulation results that highlight key relationships between noise and technology parameters. The results underline trends in noise based on current roadmap predictions and reinforce the importance of early planning of global power grids.