Maximum current estimation in CMOS circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Emerging power management tools for processor design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Noise considerations in circuit optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Hierarchical analysis of power distribution networks
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
Fast analysis and optimization of power/ground networks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simulation and optimization of the power distribution network in VLSI circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Technology trends in power-grid-induced noise
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Congestion-driven codesign of power and signal networks
Proceedings of the 39th annual Design Automation Conference
Impact of Technology in Power-Grid-Induced Noise
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
On-chip power supply network optimization using multigrid-based technique
Proceedings of the 40th annual Design Automation Conference
Analysis and Optimization of Power Grids
IEEE Design & Test
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DEPOGIT: dense power-ground interconnect architecture for physical design integrity
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
3D module placement for congestion and power noise reduction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Supply Voltage Degradation Aware Analytical Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
VLSI on-chip power/ground network optimization considering decap leakage currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient decoupling capacitor planning via convex programming methods
Proceedings of the 2006 international symposium on Physical design
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming
Proceedings of the 43rd annual Design Automation Conference
Empire: an efficient and compact multiple-parameterized model order reduction method
Proceedings of the 2007 international symposium on Physical design
On-chip decoupling capacitance and P/G wire co-optimization for dynamic noise
Proceedings of the 44th annual Design Automation Conference
Vertical via design techniques for multi-layered P/G networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effective decap insertion in area-array SoC floorplan design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Stochastic power/ground supply voltage prediction and optimization via analytical placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New spare cell design for IR drop minimization in Engineering Change Order
Proceedings of the 46th Annual Design Automation Conference
Optimal design of the power-delivery network for multiple voltage-island system-on-chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitance efficient placement for reducing transient power supply noise
Proceedings of the 2009 International Conference on Computer-Aided Design
Thermal-aware voltage droop compensation for multi-core architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Optimization of via distribution and stacked via in multi-layered P/G networks
Integration, the VLSI Journal
EMPIRE: an efficient and compact multiple-parameterized model-order reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient decoupling capacitance optimization using piecewise polynomial models
Proceedings of the Conference on Design, Automation and Test in Europe
Reconfigurable ECO cells for timing closure and IR drop minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2012 TAU power grid simulation contest: benchmark suite and results
Proceedings of the International Conference on Computer-Aided Design
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With technology scaling, the trend for high performance integrated circuits is towards ever higher operating frequency, lower power supply voltages and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the International Technology Roadmap for Semiconductors as one of the difficult challenges. The addition of decoupling capacitances (decaps) is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement and is becoming more important as technology scales. In this paper, we propose and demonstrate an algorithm for the automated placement and sizing of decaps in ASIC-like circuits. The adjoint sensitivity method is applied to calculate the first-order sensitivity of the power grid noise with respect to every decap. We propose a fast convolution technique based on piecewise linear (PWL) compressions of the original and adjoint waveforms. Experimental results show that power grid noise can be significantly reduced after a judicious optimization of decap placement, with little change of the total chip area.