An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Proceedings of the 2002 international symposium on Physical design
WSSMP: A High-Performance Serial and Parallel Symmetric Sparse Linear Solver
PARA '98 Proceedings of the 4th International Workshop on Applied Parallel Computing, Large Scale Scientific and Industrial Problems
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
2011 TAU power grid simulation contest: benchmark suite and results
Proceedings of the International Conference on Computer-Aided Design
PowerRush: a linear simulator for power grid
Proceedings of the International Conference on Computer-Aided Design
Fast static analysis of power grids: algorithms and implementations
Proceedings of the International Conference on Computer-Aided Design
On the preconditioner of conjugate gradient method: a power grid simulation perspective
Proceedings of the International Conference on Computer-Aided Design
PGT_SOLVER: an efficient solver for power grid transient analysis
Proceedings of the International Conference on Computer-Aided Design
PowerRush: efficient transient simulation for power grid analysis
Proceedings of the International Conference on Computer-Aided Design
Parallel forward and back substitution for efficient power grid simulation
Proceedings of the International Conference on Computer-Aided Design
PGT_SOLVER: an efficient solver for power grid transient analysis
Proceedings of the International Conference on Computer-Aided Design
Parallel forward and back substitution for efficient power grid simulation
Proceedings of the International Conference on Computer-Aided Design
Scalable power grid transient analysis via MOR-assisted time-domain simulations
Proceedings of the International Conference on Computer-Aided Design
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Although power grid analysis has been an active research area for a number of years, increasing chip size has exposed new challenges in this traditional topic. The simulation of these large scale networks is becoming a dominant step in the design verification flow and it often requires the very largest computer available to the design team. To spur academic research in this vital verification step, the IBM Austin Research Laboratory, with support from the ACM TAU Workshop, has successfully organized two annual TAU Power Grid Simulation Contests, and over twenty university teams across the world have participated. For 2012, the contest is focused on dynamic analysis and parallel implementation. In this paper, the organizers review the TAU 2012 Power Grid Simulation Contest. This contest was held to seek new efficient methods with parallel implementation for performing dynamic (i.e. time domain) analysis for large power grid networks. Accuracy, run-time and memory consumption were used as metrics to evaluate the various contestants, and prizes were accordingly awarded to the top three teams. The benchmarks in [1] were expanded to be suitable for dynamic analysis. These are made public, along with the scores from various teams that participated in the contest, in order to further encourage their use in future research on this important topic.