Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Proceedings of the 2002 international symposium on Physical design
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
On-chip power supply network optimization using multigrid-based technique
Proceedings of the 40th annual Design Automation Conference
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Partitioning-based approach to fast on-chip decap budgeting and minimization
Proceedings of the 42nd annual Design Automation Conference
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming
Proceedings of the 43rd annual Design Automation Conference
Hierarchical analysis of power distribution networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Decap allocation are the primary methods for addressing the dynamic voltage noise problem of on-chip power networks. When space in the immediate proximity of a hot spot is constrained, simply adding decoupling capacitance without improving the local wiring is ineffective. Based on this key observation we proposed an effecient co-optimization of decap allocation and local wiring enhancement. The method solves a linear program (LP) iteratively and is based on the decap budgeting algorithm [10]. Experimental results on two actual chip designs demonstrate the area and run-time efficiency of the co-optimization algorithm. Moreover, it provides excellent solutions even in cases where decap allocation alone fails to provide a feasible solution.