Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Proceedings of the 2002 international symposium on Physical design
On-chip power supply network optimization using multigrid-based technique
Proceedings of the 40th annual Design Automation Conference
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Partitioning-based approach to fast on-chip decap budgeting and minimization
Proceedings of the 42nd annual Design Automation Conference
Hierarchical analysis of power distribution networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-chip decoupling capacitance and P/G wire co-optimization for dynamic noise
Proceedings of the 44th annual Design Automation Conference
Efficient decoupling capacitance budgeting considering operation and process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Optimal design of the power-delivery network for multiple voltage-island system-on-chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitance efficient placement for reducing transient power supply noise
Proceedings of the 2009 International Conference on Computer-Aided Design
Parallel hierarchical cross entropy optimization for on-chip decap budgeting
Proceedings of the 47th Design Automation Conference
Decoupling capacitor planning with analytical delay model on RLC power grid
Proceedings of the Conference on Design, Automation and Test in Europe
An efficient decoupling capacitance optimization using piecewise polynomial models
Proceedings of the Conference on Design, Automation and Test in Europe
On-chip power network optimization with decoupling capacitors and controlled-ESRs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Runtime resonance noise reduction with current prediction enabled frequency actuator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a novel and efficient charge-based decoupling capacitance budgeting algorithm. Our method uses the macromodeling technique and effective radius of decoupling capacitance to reduce the size of the problem. We formulate the nonlinear optimization into a linear program (LP) by integrating the nodal equations across a time period of interest and through certain approximations. To reduce the error caused by linearization, we do multiple iterations of the linear program. Experimental results demonstrate that, with the proposed algorithm, even very large power networks (eg. 5 million nodes) can be optimized in a couple of hours with 1-2 transient analyses. Comparison of our algorithm with another heuristic method shows area efficiency and run time advantage of our method.