Vector generation for maximum instantaneous current through supply lines for CMOS circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Estimation of maximum current envelope for power bus analysis and design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Full-chip verification methods for DSM power distribution systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Estimation of maximum power supply noise for deep sub-micron designs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Computer Methods for Circuit Analysis and Design
Computer Methods for Circuit Analysis and Design
Design of an efficient power distribution network for the UltraSPARC-I microprocessor
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical power supply noise evaluation for early power grid design prediction
Proceedings of the 2001 international workshop on System-level interconnect prediction
Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
Maximum voltage variation in the power distribution network of VLSI circuits with RLC models
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Proceedings of the 2002 international symposium on Physical design
Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows
Analog Integrated Circuits and Signal Processing
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Supply Voltage Degradation Aware Analytical Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Floorplanning with power supply noise avoidance
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Gibbs sampling in power grid analysis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
VLSI on-chip power/ground network optimization considering decap leakage currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient decoupling capacitor planning via convex programming methods
Proceedings of the 2006 international symposium on Physical design
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Journal of Computer Science and Technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Noise minimization during power-up stage for a multi-domain power network
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Stochastic power/ground supply voltage prediction and optimization via analytical placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predicting the worst-case voltage violation in a 3D power network
Proceedings of the 11th international workshop on System level interconnect prediction
A Parallel Simulated Annealing Approach for Floorplanning in VLSI
ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing
Efficient power network analysis considering multidomain clock gating
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel approach to voltage-drop aware placement in large socs in advanced technology nodes
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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In this paper, we present simulation techniques to estimate the worst-case voltage variation using a RC model for the power distribution network. Pattern independent maximum envelope currents are used as a periodic input for performing the frequency-domain steady-state simulation of the linear RC circuit to evaluate the worst-case instantaneous voltage drop for the RC power distribution networks. The proposed technique unlike existing techniques, is guaranteed to give the maximum voltage drop at nodes in the RC power distribution network. We present experimental results to compare the frequency-domain and time-domain simulation techniques for estimating the maximum instantaneous voltage drop. We also present frequency domain sensitivity analysis based decoupling capacitance placement for reducing the voltage variation in the power distribution network. Experimental results on circuits extracted from layout are presented to validate the simulation and optimization techniques.