Efficient power network analysis considering multidomain clock gating

Authors:
Wanping Zhang;Wenjian Yu;Xiang Hu;Ling Zhang;Rui Shi;He Peng;Zhi Zhu;Lew Chua-Eoan;Rajeev Murgai;Toshiyuki Shibuya;Noriyuki Ito;Chung-Kuan Cheng
Affiliations:
Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA and Qualcomm Inc., San Diego, CA;Department of Computer Science and Technology, Tsinghua University, Beijing, China;Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA;Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA;Synopsys, Inc., Mountain View, CA and Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA;Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA;Qualcomm Inc., San Diego, CA;Qualcomm Inc., San Diego, CA;Magma Design Automation, Inc., San Jose, CA;Fujitsu Laboratories of America, Inc., Sunnyvale, CA;Fujitsu Laboratories Ltd., Kawasaki, Japan;Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

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Abstract

In this paper, an efficient framework is proposed to analyze the worst case of voltage variation of power network considering multidomain clock gating. First, a frequency-domain-based simulation method is proposed to obtain the time-domain voltage response. With the vector fitting technique, the frequency-domain responses are approximated by a partial fraction expression, which can be easily converted to a time-domain waveform. Then, an algorithm is proposed to find the worst-case voltage variation and corresponding clock gating patterns, through superimposing the voltage responses caused by all domains working separately. The major computation of the whole framework is solving the frequency-domain equation system, whose complexity is about O(NαD log fmax), where α is between one and two if using an iterative solver from the PETSc library. N is the node number, fmax is the upper bound of frequency, and D is the number of clock domains. Numerical results show that the proposed simulation method is up to several hundred times faster than commercial fast simulators, like HSPICE and MSPICE. In addition, the proposed method is able to analyze large-scale power networks that the commercial tools are not able to afford.