Iterative methods and parallel computation for power systems
Iterative methods and parallel computation for power systems
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Full-chip verification methods for DSM power distribution systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hierarchical analysis of power distribution networks
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Model and analysis for combined package and on-chip power grid simulation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Iterative Methods for Sparse Linear Systems
Iterative Methods for Sparse Linear Systems
Proceedings of the 39th annual Design Automation Conference
Modeling and analysis of regular symmetrically structured power/ground distribution networks
Proceedings of the 39th annual Design Automation Conference
INDUCTWISE: inductance-wise interconnect simulator and extractor
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Power network analysis using an adaptive algebraic multigrid approach
Proceedings of the 40th annual Design Automation Conference
Efficient power/ground network analysis for power integrity-driven design methodology
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An unconditional stable general operator splitting method for transistor level transient analysis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Efficient early stage resonance estimation techniques for C4 package
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
RCLK-VJ network reduction with Hurwitz polynomial approximation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Analysis of buffered hybrid structured clock networks
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient transient simulation for transistor-level analysis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Relaxed hierarchical power/ground grid analysis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Floorplan and power/ground network co-synthesis for fast design convergence
Proceedings of the 2006 international symposium on Physical design
High accurate pattern based precondition method for extremely large power/ground grid analysis
Proceedings of the 2006 international symposium on Physical design
An Improved AMG-based Method for Fast Power Grid Analysis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Large power grid analysis using domain decomposition
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Large scale RLC circuit analysis using RLCG-MNA formulation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Journal of Computer Science and Technology
Accurate power grid analysis with behavioral transistor network modeling
Proceedings of the 2007 international symposium on Physical design
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
Proceedings of the conference on Design, automation and test in Europe
Large scale P/G grid transient simulation using hierarchical relaxed approach
Integration, the VLSI Journal
Parallel domain decomposition for simulation of large-scale power grids
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficient representation and analysis of power grids
Proceedings of the conference on Design, automation and test in Europe
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Incremental and on-demand random walk for iterative power distribution network analysis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
GPU friendly fast Poisson solver for structured power grid network analysis
Proceedings of the 46th Annual Design Automation Conference
Efficient power network analysis considering multidomain clock gating
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scaling power/ground solvers on multi-core with memory bandwidth awareness
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the 47th Design Automation Conference
An efficient dual algorithm for vectorless power grid verification under linear current constraints
Proceedings of the 47th Design Automation Conference
Parallel hierarchical cross entropy optimization for on-chip decap budgeting
Proceedings of the 47th Design Automation Conference
Efficient simulation of power grids
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Efficient power grid integrity analysis using on-the-fly error check and reduction
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
More realistic power grid verification based on hierarchical current and power constraints
Proceedings of the 2011 international symposium on Physical design
Parallel and scalable transient simulator for power grids via waveform relaxation (PTS-PWR)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient incremental analysis of on-chip power grid via sparse approximation
Proceedings of the 48th Design Automation Conference
PowerRush: a linear simulator for power grid
Proceedings of the International Conference on Computer-Aided Design
Fast static analysis of power grids: algorithms and implementations
Proceedings of the International Conference on Computer-Aided Design
Fast Poisson solver preconditioned method for robust power grid analysis
Proceedings of the International Conference on Computer-Aided Design
Power grid analysis with hierarchical support graphs
Proceedings of the International Conference on Computer-Aided Design
Vectorless verification of RLC power grids with transient current constraints
Proceedings of the International Conference on Computer-Aided Design
A hierarchical matrix inversion algorithm for vectorless power grid verification
Proceedings of the International Conference on Computer-Aided Design
Efficient simulation of power/ground networks with package and vias
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A silicon-validated methodology for power delivery modeling and simulation
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Deterministic random walk preconditioning for power grid analysis
Proceedings of the International Conference on Computer-Aided Design
Efficient parallel power grid analysis via additive Schwarz method
Proceedings of the International Conference on Computer-Aided Design
PowerRush: efficient transient simulation for power grid analysis
Proceedings of the International Conference on Computer-Aided Design
Parallel forward and back substitution for efficient power grid simulation
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the Conference on Design, Automation and Test in Europe
Voltage propagation method for 3-D power grid analysis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Incremental transient simulation of power grid
Proceedings of the 2014 on International symposium on physical design
Scalable power grid transient analysis via MOR-assisted time-domain simulations
Proceedings of the International Conference on Computer-Aided Design
Parallel power grid analysis using preconditioned GMRES solver on CPU-GPU platforms
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
In this paper, we propose preconditioned Krylov-subspace iterative methods to perform efficient DC and transient simulations for large-scale linear circuits with an emphasis on power delivery circuits. We also prove that a circuit with inductors can be simplified from MNA to NA format, and the matrix becomes an s.p.d matrix. This property makes it suitable for the conjugate gradient with incomplete Cholesky decomposition as the preconditioner, which is faster than other direct and iterative methods. Extensive experimental results on large-scale industrial power grid circuits show that our method is over 200 times faster for DC analysis and around 10 times faster for transient simulation compared to SPICE3. Furthermore, our algorithm reduces over 75% of memory usage than SPICE3 while the accuracy is not compromised.