Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods
Proceedings of the 38th annual Design Automation Conference
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Proceedings of the 2003 international symposium on Low power electronics and design
Exploiting Resonant Behavior to Reduce Inductive Noise
Proceedings of the 31st annual international symposium on Computer architecture
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Multiple clock and voltage domains for chip multi processors
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Thermal-aware voltage droop compensation for multi-core architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation
Proceedings of the 47th Design Automation Conference
Proceedings of the Conference on Design, Automation and Test in Europe
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
The alarms project: a hardware/software approach to addressing parameter variations
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated di/dt stressmark generation for microprocessor power delivery networks
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Decoupling for power gating: sources of power noise and design strategies
Proceedings of the 48th Design Automation Conference
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 39th Annual International Symposium on Computer Architecture
Minimizing power supply noise through harmonic mappings in networks-on-chip
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design analysis of IC power delivery
Proceedings of the International Conference on Computer-Aided Design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
AUDIT: Stress Testing the Automatic Way
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Power gating topologies in TSV based 3D integrated circuits
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
RESP: a robust physical unclonable function retrofitted into embedded SRAM array
Proceedings of the 50th Annual Design Automation Conference
Role of power grid in side channel attack and power-grid-aware secure design
Proceedings of the 50th Annual Design Automation Conference
On the potential of 3D integration of inductive DC-DC converter for high-performance power delivery
Proceedings of the 50th Annual Design Automation Conference
IR-drop in on-chip power distribution networks of ICs with nonuniform power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of power supply variations. These variations, primarily due to fast changes in supply current, can be attributed to architectural gating events that reduce power dissipation. In order to study this problem, we propose a fine-grain, parameterizable model for power-delivery networks that allows system designers to study localized, on-chip supply fluctuations in high-performance microprocessors. Using this model, we analyze voltage variations in the context of next-generation chip-multiprocessor (CMP) architectures using both real applications and synthetic current traces. We find that the activity of distinct cores in CMPs present several new design challenges when considering power supply noise, and we describe potentially problematic activity sequences that are unique to CMP architectures.