Noise considerations in circuit optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Algorithm 856: APPSPACK 4.0: asynchronous parallel pattern search for derivative-free optimization
ACM Transactions on Mathematical Software (TOMS)
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
Proceedings of the conference on Design, automation and test in Europe
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Optimal design of the power-delivery network for multiple voltage-island system-on-chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation
Proceedings of the 47th Design Automation Conference
High power-supply-rejection (PSR) current-mode low-dropout (LDO) regulator
IEEE Transactions on Circuits and Systems II: Express Briefs
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal decoupling capacitor sizing and placement for standard-cell layout designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-chip power-supply network optimization using multigrid-based technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation
Analog Integrated Circuits and Signal Processing
Proceedings of the International Conference on Computer-Aided Design
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Modern IC power delivery systems encompass large on-chip passive power grids and active on-chip or off-chip voltage converters and regulators. While there exists little work targeting on holistic design of such complex IC subsystems, the optimal system-level design of power delivery is critical for achieving power integrity and power efficiency. In this article, we conduct a systematic design analysis on power delivery networks that incorporate Buck Converters (BCs) and on-chip Low-Dropout voltage regulators (LDOs) for the entire chip power supply. The electrical interactions between active voltage converters, regulators as well as passive power grids and their influence on key system design specifications are analyzed comprehensively. With the derived design insights, the system-level codesign of a complete power delivery network is facilitated by a proposed automatic optimization flow in which key design parameters of buck converters and on-chip LDOs as well as on-chip decoupling capacitance are jointly optimized. The experimental results demonstrate significant performance improvements resulted from the proposed system cooptimization in terms of achievable area overhead, supply noise and power efficiency. Impacts of different decoupling capacitance technologies are also investigated.