A unified design methodology for CMOS tapered buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power design challenges for the decade (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
MONOLITHIC DC-DC CONVERTER ANALYSIS AND MOSFET GATE VOLTAGE OPTIMIZATION
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages
Analog Integrated Circuits and Signal Processing
Decoupling capacitors for multi-voltage power distribution systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-efficient pulse width modulation DC/DC converters with zero voltage switching control
Proceedings of the 2006 international symposium on Low power electronics and design
A monolithic buck DC-DC converter with on-chip PWM circuit
Microelectronics Journal
Fully monolithic cellular buck converter design for 3-D power delivery
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 200-mA, 93% peak power efficiency, single-inductor, dual-output DC---DC buck converter
Analog Integrated Circuits and Signal Processing
On-chip point-of-load voltage regulator for distributed power supplies
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A design methodology for integrated inductor-based DC-DC converters
Microelectronics Journal
Design analysis of IC power delivery
Proceedings of the International Conference on Computer-Aided Design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Active filter-based hybrid on-chip DC-DC converter for point-of-load voltage regulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simuiltaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage convers on from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm2 assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulatior at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-VDD microprocessor is demonstrated to be feasible.