IR-drop in on-chip power distribution networks of ICs with nonuniform power consumption

Authors:
Josep Rius
Affiliations:
Department of Electronic Engineering, Universitat Politecnica de Catalunya, Barcelona, Spain
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2013

Citing 14
Cited 0

On-chip decoupling capacitor optimization using architectural level prediction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal planning for mesh-based power distribution

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
P/G Pad Placement Optimization: Problem Forumulation for Best IR Drop

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Fast flip-chip power grid analysis via locality and grid shells

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient Design and Analysis of Robust Power Distribution Meshes

VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
VLSI on-chip power/ground network optimization considering decap leakage currents

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Novel and Efficient IR-Drop Models for Designing Power Distribution Network for Sub-100nm Integrated Circuits

ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network

Proceedings of the conference on Design, automation and test in Europe
Power Grid Physics and Implications for CAD

IEEE Design & Test
Fast Placement Optimization of Power Supply Pads

ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Power Distribution Networks with On-Chip Decoupling Capacitors

Power Distribution Networks with On-Chip Decoupling Capacitors
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design

Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

A compact IR-drop model for on-chip power distribution networks in array and wire-bonded ICs is analyzed. Chip dimensions, size, and location of the supply pads, metal coverage, piecewise distribution of IC consumption, and the resistance between the pads and the power supply are considered to obtain closed-form expressions for the IR-drop. The IR-drop model is validated by comparing its results with electrical simulations. The obtained error is in the range of 1%.